Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate, such as a wafer, using a large number of fabrication processes to form various features and multiple levels of the devices. For example, lithography is a fabrication process that involves transferring a pattern from a reticle/mask to a resist arranged on a wafer. Additional examples of fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation.
As used throughout the present disclosure, the term “wafer” generally refers to substrates formed of a semiconductor or non-semiconductor material. For example, a semiconductor or non-semiconductor material may include, but is not limited to, monocrystalline silicon, gallium arsenide or indium phosphide. A wafer may include one or more layers. For example, such layers may include, but are not limited to, a resist, a dielectric material, a conductive material, and a semiconductive material. Many different types of such layers are known in the art, and the term wafer as used herein is intended to encompass a wafer on which all types of such layers may be formed. One or more layers formed on a wafer may be patterned or unpatterned. For example, a wafer may include a plurality of dies, each having repeatable patterned features. Formation and processing of such layers of material may ultimately result in completed devices. Many different types of devices may be formed on a wafer, and the term wafer as used herein is intended to encompass a wafer on which any type of device known in the art may be fabricated.
Metrology processes are used at various steps during a semiconductor manufacturing process to monitor process control during device fabrication. Types of metrology process used for process control include overlay metrology, critical dimension (CD) metrology, wafer geometry metrology and etc. For example, during a process step, such as a lithographic processing step, overlay error may occur between a current and previous layer of the semiconductor device. Overlay is defined as the misregistration between the current layer of a semiconductor device and one or multiple previous layers of the semiconductor device. Overlay errors can arise for various reasons, including lithography tool (scanner) errors, wafer geometry induced errors, etch induced errors and the like. In order to control overlay and minimize overlay errors during fabrication of a semiconductor device, a feedback control system is applied. Feedback control system rely on i) measuring overlay using a metrology tool; ii) calculating the scanner correctables that would minimize overlay; and iii) feeding these corrections back through an advanced process control (APC) algorithm. Conventional overlay control schemes rely on measuring a fixed subset of overlay targets (i.e., static sampling plan) on the wafers for modeling overlay errors and calculating the scanner correctables.
Previous applications of overlay metrology use static sampling plans, where every wafer measured in every lot receives the same sampling plan. In this case, the sampling plan represents a selected subset of all available overlay targets on the wafers. As a result, it is often the case that a periodic “dense map” measurement is performed, where some wafers are measured using a very dense overlay sampling plan (e.g., thousands of targets), so that field-by-field corrections can be generated. These periodic measurements take time and effort. In addition, this procedure must be repeated in order to correct for significantly irregular and high order overlay signatures. Additional approaches include relying on an advanced field-by-field extrapolated modeling technique, where information from the static sampling plan is used to calculate field-by-field corrections without relying on periodic dense map measurements. Such an approach requires extensive optimization and a careful setup. In addition, extrapolation techniques are less useful for some irregular overlay signatures.
As the dimensions of semiconductor devices decrease, metrology processes become even more important to the successful manufacture of acceptable semiconductor devices. As such, it would be advantageous to provide a system and method that provides improved metrology capabilities and cures the deficiencies of prior approaches as identified above.